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INTEGRATED CIRCUITS
DATA SHEET
PCF2105 LCD controller/driver
Product specification Supersedes data of 1997 Dec 08 File under Integrated Circuits, IC12 1998 Jul 30
Philips Semiconductors
Product specification
LCD controller/driver
CONTENTS 1 2 3 3.1 3.2 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 9 9.1 9.2 9.3 9.3.1 9.3.2 FEATURES APPLICATIONS GENERAL DESCRIPTION Packages Available types ORDERING INFORMATION BLOCK DIAGRAM PINNING PAD FUNCTIONS RS: Register Select (parallel control) R/W: read/write (parallel control) E: data bus clock (parallel control) DB7 to DB0: data bus (parallel control) C60 to C1: column driver outputs R32 to R1: row driver outputs VLCD: LCD power supply OSC: oscillator SCL: serial clock line SDA: serial data line SA0: address input T1: test input FUNCTIONAL DESCRIPTION LCD bias voltage generator Oscillator External clock Power-on reset Registers Busy flag Address Counter (AC) Display Data RAM (DDRAM) Character Generator ROM (CGROM) Character Generator RAM (CGRAM) Cursor control circuit Timing generator LCD row and column drivers Programming of the MUX rate 1 : 16 Programming of the MUX rate 1 : 32 Reset function INSTRUCTIONS Clear display Return home Entry mode set I/D S 9.4 9.4.1 9.4.2 9.4.3 9.5 9.6 9.6.1 9.6.2 9.7 9.8 9.9 9.10 9.11 10 11 11.1 11.2 11.3 11.4 11.5 11.6 12 13 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19 20 21
PCF2105
Display control D C B Cursor/display shift Function set DL (parallel mode only) N and M Set CGRAM address Set DDRAM address Read busy flag and address Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) Characteristics of the I2C-bus Bit transfer START and STOP conditions System configuration Acknowledge I2C-bus protocol LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS TIMING DIAGRAMS APPLICATION INFORMATION 4-bit operation, 2 x 12 display using internal reset 8-bit operation, 2 x 12 display using internal reset 8-bit operation, 2 x 24 display I2C-bus operation, 2 x 12 display Initializing by instruction BONDING PAD LOCATIONS DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1998 Jul 30
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Philips Semiconductors
Product specification
LCD controller/driver
1 FEATURES
PCF2105
* Single chip Liquid Crystal Display (LCD) controller/driver * 1 or 2-line display of up to 24 characters per line, or 2 or 4-line display of up to 12 characters per line * 5 x 7 character format plus cursor; 5 x 8 for kana (Japanese syllabary) and user-defined symbols * On-chip generation of intermediate LCD bias voltages * On-chip oscillator requires no external components (external clock also possible) * Display data RAM: 80 characters * Character generator ROM: 240 characters * Character generator RAM: 16 characters * 4 or 8-bit parallel bus or 2-wire I2C-bus interface (400 kHz) * CMOS and TTL compatible * 32 row, 60 column outputs * Multiplex (MUX) rates 1 : 32 and 1 : 16 * Uses common 11-code instruction set * Logic supply voltage range: VDD - VSS = 2.5 to 6 V * Display supply voltage range: VDD - VLCD = 3.5 to 9 V * Low power consumption * I2C-bus address selection (SA0): 011101. 2 APPLICATIONS Furthermore, a fast I2C-bus interface (400 kHz) is provided. The PCF2105 is optimized for chip-on-glass applications. A specific letter code `M' for a character set is programmed in the Character Generator ROM (CGROM) (see Fig.5). The PCF2105 is a low power CMOS LCD controller/driver, designed to drive a split screen dot matrix LCD of 1 or 2 lines by 24 characters or 2 or 4 lines by 12 characters with a 5 x 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages which results in a minimum of external components and lower system power consumption. To allow partial VDD shutdown the ESD protection system of the SCL and SDA pads does not use a diode connected to VDD. The chip contains a character generator and displays alphanumeric and kana characters. The PCF2105 interfaces to most microcontrollers via a 4 or 8-bit parallel bus, or via the 2-wire I2C-bus. 3.1 Packages
* Telecom equipment * Portable instruments * Point-of-sale terminals. 3 GENERAL DESCRIPTION
* PCF2105MU/2: chip with bumps in tray. 3.2 Available types
* PCF2105MU/2: character set `M' in CGROM.
The PCF2105 integrated circuit is similar to the PCF2114x (described in the "PCF2116 family" data sheet) but does not contain the high voltage generator of that device. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF2105MU/2 - chip with bumps in tray DESCRIPTION VERSION -
1998 Jul 30
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Philips Semiconductors
Product specification
LCD controller/driver
5 BLOCK DIAGRAM
PCF2105
handbook, full pagewidth
C60 to C1 21 to 80 60 111 BIAS VOLTAGE GENERATOR COLUMN DRIVERS 6 60
R32 to R1
(1)
32 ROW DRIVERS 32 SHIFT REGISTER 32-BIT
V LCD
DATA LATCHES 60 SHIFT REGISTER 5 x 12-bit 5 CURSOR + DATA CONTROL 2 CHARACTER GENERATOR RAM (CGRAM) 16 CHARACTERS 5 CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS
PCF2105
VDD V SS
4
OSCILLATOR
1
OSC
T1
101
8 DISPLAY DATA RAM (DDRAM) 80 CHARACTERS 7 ADDRESS COUNTER (AC) 7 INSTRUCTION DECODER 8 DATA REGISTER (DR) 8 7 BUSY FLAG 8 INSTRUCTION REGISTER (IR) 8 I/O BUFFER 8 102 to 109 DB7 to DB0 E 98 100 R/W 99 RS 97 SCL 7
TIMING GENERATOR
DISPLAY ADDRESS COUNTER
POWER - ON RESET
110 SDA
3
MGK846
SA0
(1) Pads 5 to 8 and 9 to 12 correspond with symbols R8 to R5 and R32 to R29. Pads 13 to 20 and 81 to 88 correspond with symbols R24 to R17 and R9 to R16. Pads 89 to 92 and 93 to 96 correspond with symbols R25 to R28 and R1 to R4.
Fig.1 Block diagram.
1998 Jul 30
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Philips Semiconductors
Product specification
LCD controller/driver
6 PINNING SYMBOL OSC VDD SA0 VSS R8 to R5 R32 to R29 R24 to R17 C60 to C1 R9 to R16 R25 to R28 R1 to R4 SCL E RS R/W T1 DB7 to DB0 SDA VLCD 7 7.1 PAD FUNCTIONS RS: Register Select (parallel control) PAD 1 2 3 4 5 to 8 9 to 12 13 to 20 21 to 80 81 to 88 89 to 92 93 to 96 97 98 99 100 101 102 to 109 110 111 I/O I - I - O O O O O O O I I I I I I/O I/O I logic supply voltage I2C-bus address selection input logic ground LCD row driver outputs LCD row driver outputs LCD row driver outputs LCD column driver outputs LCD row driver outputs LCD row driver outputs LCD row driver outputs I2C-bus serial clock input data bus clock input register select input read/write input test input 8-bit bidirectional data bus input/output I2C-bus serial data input/output LCD supply voltage input 7.4 DESCRIPTION oscillator/external clock input
PCF2105
DB7 to DB0: data bus (parallel control)
Bit RS selects the register to be accessed for read and write when the device is controlled by the parallel interface. RS = 0 selects the instruction register for write and the busy flag and address counter for read. RS = 1 selects the data register for both read and write. There is an internal pull-up resistor on pad RS. 7.2 R/W: read/write (parallel control)
The bidirectional, 3-state data bus transfers data between the system controller and the PCF2105. DB7 acts as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations, DB7 to DB4 are used and DB3 to DB0 must be left open-circuit. There is an internal pull-up resistor on each of the data lines. Note that pads DB7 to DB0 must be left open-circuit when I2C-bus control is used. 7.5 C60 to C1: column driver outputs
R/W selects either the read (R/W = 1) or write (R/W = 0) operation when control is by the parallel interface. There is an internal pull-up resistor on pad R/W. 7.3 E: data bus clock (parallel control)
Pads C60 to C1 output the data for pairs of columns. This arrangement permits optimized Chip-On-Glass (COG) layout for 4-line by 12 characters. 7.6 R32 to R1: row driver outputs
Pad E should be HIGH to signal the start of a read or write operation when the device is controlled by the parallel interface. Data is clocked in or out of the chip on the falling edge of the clock. Note that pad E must be connected to VSS (logic 0) when I2C-bus control is used.
Pads R32 to R1 output the row select waveforms to the left and right halves of the display. 7.7 VLCD: LCD power supply
Negative power supply for the liquid crystal display.
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Philips Semiconductors
Product specification
LCD controller/driver
7.8 OSC: oscillator 8.2 Oscillator
PCF2105
When the on-chip oscillator is used, pad OSC must be connected to VDD. An external clock signal, if used, is input at pad OSC. 7.9 SCL: serial clock line
The on-chip oscillator provides the clock signal for the display system. No external components are required. Pad OSC must be connected to VDD. 8.3 External clock
Pad SCL is input for the I2C-bus clock signal. 7.10 SDA: serial data line
Pad SDA is input/output for the I2C-bus data line. 7.11 SA0: address input
If an external clock is to be used, it must be input at pad OSC. The resulting display frame frequency is given f osc by f frame = -----------2304 A clock signal must always be present, otherwise the LCD may be frozen in a DC state. 8.4 Power-on reset
The hardware subaddress line is used to program the device subaddress for 2 different PCF2105s on the same I2C-bus. 7.12 T1: test input
The Power-on reset block initializes the chip after power-on or power failure. 8.5 Registers
Pad T1 must be connected to VSS. Not user accessible. 8 FUNCTIONAL DESCRIPTION
Figure 1 shows the block diagram for the PCF2105. Details are explained in subsequent sections. 8.1 LCD bias voltage generator
The PCF2105 has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select (RS) signal determines which register will be accessed. The IR stores instruction codes such as `clear display' and `cursor shift', and address information for the DDRAM and CGRAM. The system controller can write data to but can not read data from the instruction register. The DR temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM (corresponding to the address in the address counter) is written to the DR prior to being read by the `read data' instruction. 8.6 Busy flag
The intermediate bias voltages for the LCD are generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system power consumption. The optimum levels depend on the multiplex (MUX) rate and are selected automatically when the number of lines in the display is defined. The optimum value of the LCD operating voltage VOP depends on the MUX rate, the LCD threshold voltage Vth and the number of bias levels. The relationships, together with the discrimination ratio (D) are given in Table 1. Using a 5-level bias scheme for MUX rate 1 : 16 allows VOP < 5 V for most LCDs. The effect on the display contrast is negligible. Table 1 MUX RATE 1 : 16 1 : 32 Optimum values for VOP NUMBER OF BIAS LEVELS 5 6
The Busy Flag (BF) indicates the free or busy status of the PCF2105. Bit BF = 1 indicates that the chip is busy and further instructions will not be accepted. The BF is output at pad DB7 when bit RS = 0 and bit R/W = 1. Instructions should only be written after checking that BF = 0 or waiting for the required number of clock cycles. 8.7 Address Counter (AC)
v OP --------v th 3.67 5.19
V on D = --------V off 1.277 1.196
The AC assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the instructions `set CGRAM address' and `set DDRAM address'. After a read/write operation the AC is automatically incremented or decremented by 1. The AC contents are output to the bus (pads DB6 to DB0) when bit RS = 0 and bit R/W =1.
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Philips Semiconductors
Product specification
LCD controller/driver
8.8 Display Data RAM (DDRAM) 8.11 Cursor control circuit
PCF2105
The DDRAM stores up to 80 characters of display data, represented by 8-bit character codes. DDRAM locations not used for storing display data can be used as general purpose RAM. The basic DDRAM-to-display mapping scheme is shown in Fig.2. With no display shift, the characters represented by the codes in the first 12 or 24 DDRAM locations, starting at address 00 in line 1, are displayed. Subsequent lines display data starting at addresses 20, 40, or 60 hexadecimal (hex). Figures 3 and 4 show the DDRAM-to-display mapping scheme when the display is shifted. The address range for a 1-line display is 00 to 4F; for a 2-line display from 00 to 27 (line 1) and 40 to 67 (line 2); for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and 60 to 73 for lines 1, 2, 3 and 4 respectively. For 2 and 4-line displays the end address of one line and the start address of the next line are not successive. When the display is shifted each line wraps around independently of the others (see Figs 3 and 4). When data is written to the DDRAM, wrap-around occurs from 4F to 00 in 1-line display and from 27 to 40 and 67 to 00 in 2-line display; from 13 to 20, 33 to 40, 53 to 60 and 73 to 00 in 4-line display. 8.9 Character Generator ROM (CGROM)
The cursor control circuit generates the cursor (underline and/or character blink as shown in Fig.7) at the DDRAM address contained in the address counter. When the address counter contains the CGRAM address the cursor will be inhibited. 8.12 Timing generator
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 8.13 LCD row and column drivers
The PCF2105 contains 32 row drivers and 60 column drivers. They connect the appropriate LCD bias voltages in sequence to the display, in accordance with the data to be displayed. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 8 and 9 show typical waveforms. In the 1-line display (MUX rate 1 : 16), the row outputs are driven in pairs, for example R1/R17 and R2/R18. This allows the output pairs to be connected in parallel, thereby providing greater drive capability. Unused outputs should be left unconnected.
The CGROM generates 240 character patterns in 5 x 8 dot format from 8-bit character codes. Figure 5 shows the character set currently available. 8.10 Character Generator RAM (CGRAM)
Up to 16 user-defined characters may be stored in the CGRAM. The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.5). Figure 6 shows the addressing principle for the CGRAM.
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
Display handbook, 4 columns Position (decimal)
1
2
3
4
5
22 23 24
non-displayed DDRAM addresses
4C 4D 4E 4F
00 01 02 03 04
15 16 17 18 19
DDRAM Address (hex)
1-line display non-displayed DDRAM address
00 01 02 03 04 15 16 17 18 19 24 25 26 27
DDRAM Address (hex)
line 1
40 41 42 43 44
55 56 57 58 59
64 65 66 67
MLA792
line 2
2-line display
handbook, 4 columns
non-displayed DDRAM addresses 2 3 4 5 6 7 8 9 10 11 12 line 1
1
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33
line 2
DDRAM Address (hex)
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
line 3
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73
line 4
4 line display
MLA793
Fig.2 DDRAM-to-display mapping; no shift.
1998 Jul 30
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
Display Position (decimal) DDRAM Address (hex)
1
23
4
5
22 23 24
14 15 16
Display Position (decimal) DDRAM Address (hex) line 1 DDRAM Address (hex)
1
23
4
5
22 23 24
16 17 18
4F 00 01 02 03
01 02 03 04 05
1-line display
1-line display
27 00 01 02 03
14 15 16
01 02 03 04 05
16 17 18
line 1
DDRAM Address (hex)
67 40 41 42 43
54 55 56
MLA802
line 2
41 42 43 44 45
56 57 58
MLA815
line 2
2-line display
2-line display
1234567
8 9 10 11 12 line 1
12
3 4 5 6 7 8 9 10 11 12 line 1
13 00 01 02 03 04 05 06 07 08 09 0A
01 02 03 04 05 06 07 08 09 0A 0B 0C
33 20 21 22 23 24 25 26 27 28 29 2A
line 2 DDRAM Address (hex)
21 22 23 24 25 26 27 28 29 2A 2B 2C
line 2
DDRAM Address (hex)
53 40 41 42 43 44 45 46 47 48 49 4A
line 3
41 42 43 44 45 46 47 48 49 4A 4B 4C
line 3
73 60 61 62 63 64 65 66 67 68 69 6A
line 4
61 62 63 64 65 66 67 68 69 6A 6B 6C
line 4
MLA816
4-line display
MLA803
4-line display
Fig.3 DDRAM-to-display mapping; right shift.
Fig.4 DDRAM-to-display mapping; left shift.
1998 Jul 30
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
CG RAM 1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGK847
Fig.5 Character set `M' in CGROM.
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
handbook, full pagewidth
character codes (DDRAM data) 6 5 4 3 2 1 lower order bits 0 0 0 0 0 0 0 6 5
CGRAM address 4 3 2 1 lower order bits 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 higher order bits
character patterns (CGRAM data) 4 3 2 1 0
7
higher order bits 0 0 0
higher order bits 0 0
lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 2 0 0 0 0 character pattern example 1 cursor position
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
MGA800 - 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th line will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4; bit 4 being at the left end, as shown in this figure. CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data is logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the `set CGRAM address' instruction. Bit 6 can be set using the `set DDRAM address' instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `read busy flag and address' instruction.
Fig.6 Relationship between CGRAM addresses, data and display patterns.
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
cursor 5 x 7 dot character font alternating display
MGA801
cursor display example
blink display example
Fig.7 Cursor and blink display examples.
1998 Jul 30
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
handbook, full pagewidth
frame n
frame n 1
state 1 (ON) state 2 (ON)
ROW 1
VDD V2 V3 /V4 V5 V LCD VDD V2
ROW 9
V3 /V4 V5 V LCD VDD V2 V3 /V4 V5 V LCD VDD V2
1-line display (1:16)
ROW 2
COL 1
V3 /V4 V5 V LCD VDD V2 V3 /V4 V5 V LCD VOP
COL 2
0.25 VOP state 1 0 V 0.25 VOP VOP VOP
0.25 VOP state 2 0 V 0.25 VOP VOP
MGA802 - 1
123
16 1 2 3
16
Fig.8 Typical LCD waveforms; 1-line display.
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
handbook, full pagewidth
frame n V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD
frame n 1
state 1 (ON) state 2 (ON)
ROW 1
ROW 9
ROW 2
2-line display (1:32)
COL 1
COL 2
VOP
state 1
0.15 VOP 0V 0.15 VOP
VOP VOP
state 2
0.15 VOP 0V 0.15 VOP
VOP
MGA803 - 1
123
32 1 2 3
32
Fig.9 Typical LCD waveforms; 2-line display.
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Philips Semiconductors
Product specification
LCD controller/driver
8.14 Programming of the MUX rate 1 : 16
PCF2105
To program the MUX rate 1 : 16, bits M and N of the `function set' instruction must be set to logic 0 (see Table 3). Figures 10, 11 and 12 show the DDRAM addresses of the display characters. The second row of each figure corresponds to either the right half of a 1-line display or to the second line of a 2-line display. Wrap around of data during display shift or when writing data is non-standard.
With the MUX rate 1 : 16 the PCF2105 can be used in the following ways: * To drive a 1-line display of 24 characters * To drive a 2-line display of 12 characters, resulting in better contrast. The internal data flow of the chip is optimized for this purpose.
handbook, full pagewidth
display position DDRAM address
1 00
2 01
3 02
4 03
5 04
6 05
7 06
8 07
9 08
10 09
11 0A
12 0B
display position DDRAM address
13 0C
14 0D
15 0E
16 0F
17 10
18 11
19 12
20 13
21 14
22 15
23 16
24 17
MLB899
Fig.10 DDRAM-to-display mapping; no shift.
handbook, full pagewidth
display position DDRAM address
1 4F
2 00
3 01
4 02
5 03
6 04
7 05
8 06
9 07
10 08
11 09
12 0A
display position DDRAM address
13 0B
14 0C
15 0D
16 0E
17 0F
18 10
19 11
20 12
21 13
22 14
23 15
24 16
MLB900
Fig.11 DDRAM-to-display mapping; right shift.
handbook, full pagewidth
display position DDRAM address
1 01
2 02
3 03
4 04
5 05
6 06
7 07
8 08
9 09
10 0A
11 0B
12 0C
display position DDRAM address
13 0D
14 0E
15 0F
16 10
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18
MLB901
Fig.12 DDRAM-to-display mapping; left shift.
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Philips Semiconductors
Product specification
LCD controller/driver
8.15 Programming of the MUX rate 1 : 32
PCF2105
Instructions are of 4 categories, those that: 1. Designate PCF2105 functions such as display format, data length, etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. In normal use, category 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, thus enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation, no instruction other than the `read busy flag and address' will be executed. Because the busy flag is set to logic 1 while an instruction is being executed, it is advisable to ensure that the flag is set to logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 3. An instruction sent while the busy flag is HIGH will not be executed. 9.1 Clear display
With the MUX rate 1 : 32 the PCF2105 can be used in the following ways: * To drive a 2-line display of 24 characters, use instruction `function set' to set bit M to logic 0 and bit N to logic 1 * To drive a 4-line display of 12 characters, use instruction `function set' to set both bits M and N to logic 1. 8.16 Reset function
The PCF2105 automatically initializes (resets) when power is turned on. The state after reset is given in Table 2 (see Tables 3 and 4 for the description of the bits). Table 2 STEP 1 2 clear display function set: bit DL = 1: 8-bit interface bits M and N = 0: 1-line display bit G = 0: not used 3 display control: bit D = 0: display off bit C = 0: cursor off bit B = 0: blink off 4 entry mode set: bit I/D = 1: +1(increment) bit G = 0: not used 5 default address pointer to DDRAM; the busy flag indicates the busy state (BF = 1) until initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 10 and 11. I2C-bus interface reset State after reset DESCRIPTION
`Clear display' writes space code 20 (hexadecimal) into all DDRAM addresses (the character pattern for character code 20 must be a blank pattern), sets the DDRAM address counter to logic 0 and returns the display to its original position if it was shifted. Consequently, the display disappears and the cursor or blink position goes to the left edge of the display (the first line if 2 or 4 lines are displayed) and sets bit I/D of `entry mode set' to logic 1 (increment mode). Bit S of `entry mode set' does not change. The instruction `clear display' requires extra execution time. This may be allowed for checking the Busy Flag (BF) or by waiting until 2 ms has elapsed. The latter must be applied where no read-back options are available, as in some Chip-On-Glass (COG) applications. 9.2 Return home
6 9
INSTRUCTIONS
Only two PCF2105 registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers to allow interface to various types of microcontrollers which operate at different speeds or to allow interfacing to peripheral control ICs. The PCF2105 operation is controlled by the instructions shown in Table 3 together with their execution time. Details are explained in subsequent sections.
`Return home' sets the DDRAM address counter to logic 0 and returns the display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the display (the first line if 2 or 4 lines are displayed). Bits I/D and S of `entry mode set' do not change.
1998 Jul 30
16
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Jul 30 17 Function set 0 0 0 0 1 DL N M G 0 Set CGRAM address Set DDRAM address Read busy flag and address Read data Write data Notes 1. In the I2C-bus mode the DL bit is don't care. 8-bit mode is assumed. In the I2C-bus mode a control byte is required when bit RS or R/W is changed; control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0. 1 2. Example: fosc = 150 kHz, T cy = -------- = 6.67 s ; 3 cycles = 20 s; 165 cycles = 1.1 ms. f osc 0 0 0 1 1 0 0 1 1 0 0 1 BF 1 ACG ADD AC read data write data Philips Semiconductors Table 3 Instructions (note 1)
LCD controller/driver
INSTRUCTION NOP Clear display Return home
RS 0 0 0
R/W 0 0 0
DB7 0 0 0
DB6 0 0 0
DB5 0 0 0
DB4 0 0 0
DB3 0 0 0
DB2 0 0 0
DB1 0 0 1
DB0 0 1 0
DESCRIPTION no operation clears entire display and sets DDRAM address 00 in Address Counter (AC) sets DDRAM address 00 in the AC; also returns shifted display to original position; DDRAM contents remain unchanged sets cursor move direction and specifies shift of display; these operations are performed during data write and read sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B) moves cursor and shifts display without changing DDRAM contents sets interface data length (DL), number of display lines (N, M) and voltage generator control (G); bit G is not used sets CGRAM address sets DDRAM address reads BF indicating internal operation is being performed and reads AC contents reads data from CGRAM or DDRAM writes data to CGRAM or DDRAM
REQUIRED CLOCK CYCLES(2) 0 165 3
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
3
Display control
0
0
0
0
0
0
1
D
C
B
3
Cursor/display shift
0
0
0
0
0
1
S/C
R/L
0
0
3 3
3 3 0 3 3 Product specification
PCF2105
Philips Semiconductors
Product specification
LCD controller/driver
Table 4 BIT I/D S D C B S/C R/L DL N (M = 0) N (M = 1) BF Co 9.3 9.3.1 decrement display freeze display off cursor off character at cursor position does not blink cursor move left shift 4 bits 2 lines x 12 characters; MUX rate 1 : 16 reserved end of internal operation last control byte, only data bytes to follow Entry mode set I/D Command bit identities, used in Table 3 LOGIC 0 increment display shift display on cursor on character at cursor position blinks display shift right shift 8 bits 2 lines x 24 characters; MUX rate 1 : 32 4 lines x 12 characters; MUX rate 1 : 32 internal operation in progress LOGIC 1
PCF2105
next two bytes are a data byte and another control byte 9.4.3 B
When bit I/D = 1 (0), the DDRAM or CGRAM address increments (decrements) by 1 when data is written to or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor and blink are inhibited when the CGRAM is accessed. 9.3.2 S
The character indicated by the cursor blinks when bit B = 1. The blink is displayed by switching between display characters and all dots on with a period of 1 second when fosc = 150 kHz (see Fig.7). At other clock frequencies the blink period is equal to 150 kHz --------------------f osc The cursor and the blink can be set to display simultaneously. 9.5 Cursor/display shift
When bit S = 1, the entire display shifts either to the right (bit I/D = 0) or to the left (I/D = 1) during a DDRAM write. Consequently, it looks as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. When S = 0 the display does not shift. 9.4 9.4.1 Display control D
The display is on when bit D = 1 and off when D = 0. Display data in the DDRAM is not affected and can be displayed immediately by setting D to logic 1. 9.4.2 C
`Cursor/display shift' moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In the 2 or 4-line display, the cursor moves to the next line when it passes the last position of the line (40 or 20 decimal). When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the cursor shift.
The cursor is displayed when bit C = 1 and inhibited when C = 0. Even if the cursor disappears, the display functions, I/D, etc. remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.7).
1998 Jul 30
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Philips Semiconductors
Product specification
LCD controller/driver
9.6 9.6.1 Function set DL (PARALLEL MODE ONLY) 9.9 Read busy flag and address
PCF2105
Bit DL sets the interface data length. Data is sent or received in bytes (DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4) when DL = 0. When 4-bit length is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 are left open (internal pull-ups). DL can not be set to logic 0 from the I2C-bus interface. If DL has been set to logic 0 via the parallel bus, programming via the I2C-bus interface is complicated. 9.6.2 N AND M
`Read busy flag and address' reads the Busy Fag (BF). When bit BF = 1 it indicates that an internal operation is in progress. The next instruction will not be executed until BF = 0, so BF should be checked before sending another instruction. At the same time, the value of the AC expressed in binary A[6] to A[0] is read out. The address counter is used by both CGRAM and DDRAM and its value is determined by the previous instruction. 9.10 Write data to CGRAM or DDRAM
Bits N and M set the number of display lines. 9.7 Set CGRAM address
`Write data' writes binary 8-bit data (D[7] to D[0]) to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written to is determined by the previous specification of CGRAM or DDRAM address setting. After writing, the address automatically increments or decrements by 1, in accordance with the `entry mode set`. Only bits D[4] to D[0] of CGRAM data are valid, bits D[7] to D[5] are `don't care'. 9.11 Read data from CGRAM or DDRAM
`Set CGRAM address' sets bits 0 to 5 of the CGRAM address (ACG in Table 3) into the AC (binary A[5] to A[0]). Data can then be written to or read from the CGRAM. Only bits 0 to 5 of the CGRAM address are set by the `set CGRAM address' instruction. Bit 6 can be set using the `set DDRAM address' instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `read busy flag and address' instruction. 9.8 Set DDRAM address
`Read data' reads binary 8-bit data D[7] to D[0] from the CGRAM or DDRAM. The most recent `set address' instruction determines whether the CGRAM or DDRAM is to be read. The `read data' instruction gates the content of the Data Register (DR) to the bus while pad E = HIGH. After E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. Remark: the only three instructions that update the DR are: * `Set CGRAM address' * `Set DDRAM address' * `Read data' from CGRAM or DDRAM. Other instructions (e.g. `write data', `cursor/display shift', `clear display', `return home') will not change the data register content.
`Set DDRAM address' sets the DDRAM address (ADD in Table 3) into the AC (binary A[6] to A[0]). Data can then be written to or read from the DDRAM. Table 5 Hexadecimal address ranges ADDRESS 00 to 4F 00 to 0B and 0C to 4F 00 to 27 and 40 to 67 FUNCTION 1 line of 24 characters 2 lines of 12 characters 2 lines of 24 characters
00 to 13, 20 to 33, 40 to 53 4 lines of 12 characters and 60 to 73
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Philips Semiconductors
Product specification
LCD controller/driver
10 INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) The PCF2105 can send data in either two 4-bit modes or one 8-bit mode and can thus interface to 4 or 8-bit microcontrollers. In the 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. The control lines E, RS, and R/W are required. In the 4-bit mode data is transferred in two cycles of 4-bits each. The higher order bits (corresponding to DB7 to DB4
PCF2105
in 8-bit mode) are sent in the first cycle and the lower order bits (DB3 to DB0 in 8-bit mode) in the second cycle. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the busy flag check. The 4-bit mode is selected by instruction. See Figs 13, 14 and 15 for examples of bus protocol. In the 4-bit mode, the pads DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally.
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4 instruction write
IR0
AC4
AC0
DR4
DR0
busy flag and address counter read
data register read
MGA804
Fig.13 4-bit transfer example.
1998 Jul 30
20
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
AC3
not busy
AC3
D7
D3
instruction write
busy flag check
busy flag check
instruction write
MGA805
IR7 and IR3: instruction 7th bit and 3rd bit. AC3: address counter 3rd bit.
Fig.14 An example of 4-bit data transfer timing sequence.
RS
R/W
E
internal
internal operation
DB7
data instruction write
busy busy flag check
busy busy flag check
not busy busy flag check
data instruction write
MGA806
Fig.15 Example of busy flag check timing sequence.
1998 Jul 30
21
Philips Semiconductors
Product specification
LCD controller/driver
11 INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) 11.1 Characteristics of the I2C-bus 11.5 Acknowledge
PCF2105
The I2C-bus is for bidirectional, 2-line communication between different ICs or modules. The 2 lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 11.2 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH-level period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.16). 11.3 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Fig.17). 11.4 System configuration
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Fig.19). 11.6 I2C-bus protocol
A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Fig.18).
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The I2C-bus configuration for the different PCF2105 read and write cycles is illustrated in Figs 20, 21 and 22.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.16 Bit transfer.
1998 Jul 30
22
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.17 Definition of START and STOP conditions.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.18 System configuration.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.19 Acknowledgement on the I2C-bus.
1998 Jul 30
23
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acknowledgement from PCF2105 S
Philips Semiconductors
LCD controller/driver
S011101A0A1
0
CONTROL BYTE
A
DATA
A0
CONTROL BYTE
A
DATA
AP
Fig.20 Master transmits to slave receiver; write mode.
handbook, full pagewidth
24
slave address R/W Co
2n 0 bytes
1 byte Co
n 0 bytes
update data pointer
S 011101A0 0
MGK848
PCF2105 slave address
R/W
Product specification
PCF2105
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acknowledgement from PCF2105 S
Philips Semiconductors
LCD controller/driver
S011101A0A1
0
CONTROL BYTE
A
DATA
A011
CONTROL
A
DATA
(1)
A
slave address R/W Co
2n 0 bytes
2 bytes Co
acknowledgement from PCF2105
(1) Last data byte is a dummy byte (may be omitted).
Fig.21 Master reads after setting word address; write word address, set RS and R/W; read data.
handbook, full pagewidth
25
S
SLAVE ADDRESS
no acknowledgement from master
S A1A 0
DATA
A
DATA
1P
n bytes R/W
last byte update data pointer
MGK849
Product specification
PCF2105
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
handbook, full pagewidth
acknowledgement from PCF2105
acknowledgement from master
no acknowledgement from master
S
SLAVE ADDRESS
S A1A 0
DATA
A
DATA
1P
n bytes R/W
last byte update data pointer
MGK850
Fig.22 Master reads slave immediately after first byte; read mode (RS previously defined).
12 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VLCD VI(n) VO(n) II(n) IO(n) In Ptot P/out Tstg logic supply voltage LCD supply voltage input voltage on pads OSC, RS, R/W, E and DB0 to DB7 output voltage on pads R1 to R32, C1 to C60 and VLCD DC input current on every pad DC output current on every pad current on VDD, VSS and VLCD total power dissipation power dissipation per output storage temperature PARAMETER MIN. -0.5 VDD - 11 VSS - 0.5 -10 -10 -50 - - -65 MAX. +8.0 VDD VDD + 0.5 +10 +10 +50 400 100 +150 V V V V mA mA mA mW mW C UNIT
VLCD - 0.5 VDD + 0.5
13 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices" ).
1998 Jul 30
26
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
14 DC CHARACTERISTICS VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD - 3.5 to VDD - 9 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD VLCD IDD(ext) logic supply voltage LCD supply voltage external supply current note 1 VDD = 5 V; VOP = 9 V; fosc = 150 kHz; Tamb = 25 C VDD = 3 V; VOP = 5 V; fosc = 150 kHz; Tamb = 25 C II(LCD) VPOR Logic VIL VIH VIL(OSC) VIH(OSC) Ipu IOL(DB) IOH(DB) IL I2C-bus SDA and SCL VIL VIH IL Ci IOL(SDA) LOW-level input voltage HIGH-level input voltage leakage current input capacitance LOW-level output current on SDA note 3 note 3 pads set to logic 0 (VSS) or logic 1 (VDD) note 4 VOL = 0.4 V; VDD = 5 V VSS 0.7VDD -1 - 3 - - - - - 0.3VDD VDD +1 7 - V V A pF mA LOW-level input voltage on pads E, RS, R/W, DB7 to DB0 and SA0 HIGH-level input voltage on pads E, RS, R/W, DB7 to DB0 and SA0 LOW-level input voltage on pad OSC HIGH-level input voltage on pad OSC pull-up current on pads DB7 to DB0, RS and R/W LOW-level output current on pads DB7 to DB0 HIGH-level output current on pads DB7 to DB0 leakage current on pads DB7 to DB0, OSC, E, RS, R/W and SA0 pads set to logic 0 (VSS) VOL = 0.4 V; VDD = 5 V VOH = 4 V; VDD = 5 V pads set to logic 0 (VSS) or logic 1 (VDD) VSS 0.7VDD VSS 0.04 1.6 -1.0 -1 - - - 0.15 - - - 0.3VDD VDD V V input current on VLCD Power-on reset voltage level note 1 note 2 2.5 VDD - 9 - - - - 200 200 6.0 V A A VDD - 3.5 V 500 300 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
-
150
200
A
- -
50 1.3
100 1.8
A V
VDD - 1.5 V VDD 1.00 - - +1 V A mA mA A
VDD - 0.1 -
1998 Jul 30
27
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
SYMBOL LCD outputs Ro(ROW) Ro(COL) Vbias(tol) Notes
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
row output resistance on pads R32 to R1 column output resistance on pads C60 to C1 bias voltage tolerance on pads R32 to R1 and C60 to C1
note 5 note 5 note 6
- - -
1.5 3 20
3 6 130
k k mV
1. LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive; internal or external clock with duty factor 50%. 2. Resets all logic when VDD < VPOR. 3. When the voltages are above VDD or below VSS, an input current may flow; this current must not exceed 0.5 mA. 4. Tested on sample basis. 5. Resistance of output terminals (R32 to R1 and C60 to C1) with load current IL = 150 A; VOP = VDD - VLCD = 9 V; outputs measured one at a time. 6. LCD outputs open-circuit. 15 AC CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL ffr(LCD) fosc PARAMETER LCD frame frequency (internal clock) oscillator frequency (external clock) CONDITIONS note 1 MIN. 40 90 65 150 TYP. MAX. UNIT 100 225 Hz kHz
Bus timing characteristics: Parallel Interface; notes 1 and 2 WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2105); see Fig.23 Tcy(en) tW(en) tsu(A) th(A) tsu(D) th(D) Tcy(en) tW(en) tsu(A) th(A) td(D) th(D) enable cycle time enable pulse width address set-up time address hold time data set-up time data hold time 500 220 50 25 60 25 - - - - - - - - - - - - - - - - - - - - - - 150 100 ns ns ns ns ns ns
READ OPERATION (READING DATA FROM PCF2105 TO MICROCONTROLLER); see Fig.24 enable cycle time enable pulse width address set-up time address hold time data delay time data hold time 500 220 50 25 - 20 ns ns ns ns ns ns
1998 Jul 30
28
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Timing characteristics: I2C-bus interface; note 2; see Fig.25 fSCL tSW tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tSU;STO CL Notes 1. VDD = 5.0 V. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. 3. CL = total capacitance of one bus line in pF and R = 100 . 4. A fast mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. 5. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 6. The maximum tHD;DAT has only to be met if the device does not stretch tLOW of the SCL signal. SCL clock frequency tolerable spike width on bus bus free time set-up time for a repeated START condition START condition hold time SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time set-up time for STOP condition load capacitance for each bus line note 3 note 3 note 4 notes 5 and 6 - - 1.3 0.6 0.6 1.3 0.6 - - 100 0 0.6 - - - - - - - - 20 + RCL 20 + RCL - - - - 400 50 - - - - - 300 300 - 0.9 - 400 kHz ns s s s s s ns ns ns s s pF
1998 Jul 30
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Philips Semiconductors
Product specification
LCD controller/driver
16 TIMING DIAGRAMS
PCF2105
handbook, full pagewidth
RS
VIH VIL tsu(A)
VIH VIL th(A) VIL tW(en) th(A) VIH VIL th(D) VIH VIL
MGK851
R/W
VIL
E
VIL
VIH
VIL
tsu(D) DB0 to DB7 VIH VIL valid data Tcy(en)
Fig.23 Parallel bus write operation sequence; writing data from microcontroller to PCF2105.
handbook, full pagewidth
RS
VIH VIL tsu(A)
VIH VIL th(A) VIH tW(en)
R/W
VIH
th(A) VIH VIL th(D) VIL
E
VIL
VIH td(D)
DB0 to DB7
VOH VOL
VOH VOL Tcy(en)
MGK852
Fig.24 Parallel bus read operation sequence; reading data from PCF2105 to microcontroller.
1998 Jul 30
30
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PROTOCOL START CONDITION (S) BIT 7 MSB (A7) BIT 6 (A6) BIT 0 LSB R/W ACKNOWLEDGE (A) STOP CONDITION (P) SDA
handbook, full pagewidth
Philips Semiconductors
LCD controller/driver
31
t BUF t LOW tr SCL t HD;STA t HIGH tf t/fSCL
MGA811 - 1
t SU;STO
Product specification
PCF2105
Fig.25 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
Philips Semiconductors
Product specification
LCD controller/driver
17 APPLICATION INFORMATION
PCF2105
handbook, 4 columns
P20 P21 P22
RS 32 R/W E R1 to R32 to LCD 60
P80CL51
8
PCF2105
C1 to C60 DB0 to DB7
MGK853
P10 to P17
Fig.26 Direct connection to 8-bit microcontroller; 8-bit bus.
handbook, 4 columns
P10 P11 P12
RS 32 R/W E R1 to R32 to LCD 60
P80CL51
PCF2105
C1 to C60 DB4 to DB7
MGK854
P14 to P17
4
Fig.27 Direct connection to 8-bit microcontroller; 4-bit bus.
handbook, full pagewidth
VLCD 100 nF VDD 100 nF
VLCD VDD OSC
R7 to R16 R25 to R32
16
R1 to R8 R17 to R24
16
2 x 24-CHARACTER LCD DISPLAY (SPLIT SCREEN) 60 60
MGK855
PCF2105
V SS 8 DB0 to DB7 E RS R/W C1 to C60 60
VSS
Fig.28 Typical application using parallel interface.
1998 Jul 30
32
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
16
handbook, full pagewidth
VLCD 100 nF VDD 100 nF VDD VDD V SS
VLCD VDD
R1 to R16
R17 to R24 OSC 16
2 x 24-CHARACTER LCD DISPLAY (SPLIT SCREEN) 60 60
PCF2105
C1 to C60 V SS SCL SDA SA0
VDD
VLCD 100 nF VDD 100 nF
VLCD VDD R1 to R16 OSC 16
2 x 12-CHARACTER LCD DISPLAY
PCF2105
C1 to C60 60
MGK856
V SS
V SS SCL SDA SA0
VSS
SCL SDA
MASTER TRANSMITTER PCF84C81
Fig.29 Application using I2C-bus interface.
1998 Jul 30
33
Philips Semiconductors
Product specification
LCD controller/driver
17.1 4-bit operation, 2 x 12 display using internal reset 17.3 8-bit operation, 2 x 24 display
PCF2105
The program must set functions prior to 4-bit operation. Table 6 shows an example. When power is turned on, 8-bit operation is automatically selected and the PCF2105 attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB3 to DB0, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 6 step 3). Thus, DB7 to DB4 of the `function set' are written twice. 17.2 8-bit operation, 2 x 12 display using internal reset
For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the 8th character is completed (see Table 8). It should be noted that both lines of the display are always shifted together, data does not shift from one line to the other. 17.4 I2C-bus operation, 2 x 12 display
A control byte is required with most instructions (see Table 9). 17.5 Initializing by instruction
Table 7 shows an example of a 1-line display in 8-bit operation. The PCF2105 functions must be set by the `function set' instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes the display position only DDRAM contents remain unchanged. Display data entered first can be displayed when the `return home' instruction is performed.
If the power supply conditions for correctly operating the internal reset circuit are not met, the PCF2105 must be initialized by instruction. Tables 10 and 11 show how this may be performed for 8-bit and 4-bit operation.
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34
Philips Semiconductors
Product specification
LCD controller/driver
Table 6 STEP 1 Example of 4-bit operation; 1-line display; using internal reset INSTRUCTION power supply on (PCF2105 is initialized by the internal reset circuit) function set RS 0 3 RS 0 0 4 RS 0 0 5 RS 0 R/W DB7 DB6 DB5 DB4 0 0 0 1 0 DISPLAY OPERATION initialized; no display appears
PCF2105
2
sets to 4-bit operation; in this instance operation is handled as 8-bits by initialization and only this instruction completes with one write
function set R/W DB7 DB6 DB5 DB4 0 0 0 0 0 0 1 0 0 0 sets to 4-bit operation; selects 2 x 12 display 4-bit operation starts from this point and resetting is needed
display control R/W DB7 DB6 DB5 DB4 0 0 0 1 0 1 0 1 0 0 _ turns display and cursor on entire display is blank after initialization
entry mode set R/W DB7 DB6 DB5 DB4 0 0 0 0 0 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM display is not shifted
0 6 RS 1 1
0
0
1
1
0
write data to CGRAM or DDRAM R/W DB7 DB6 DB5 DB4 0 0 1 0 1 1 0 1 1 0 P_ writes `P'; the DDRAM has already been selected by initialization at power-on the cursor is incremented by 1 and shifted to the right
1998 Jul 30
35
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Jul 30 36 Philips Semiconductors Table 7 STEP 1 2 Example of 8-bit operation; 1-line display; using internal reset (character set `M')
LCD controller/driver
INSTRUCTION power supply on (PCF2105 is initialized by the internal reset function) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 0 0 0 0 _ 0 0 0 1 1 1 0 _ 0 0 0 0 1 1 0
DISPLAY
OPERATION initialized; no display appears sets to 8-bit operation; selects 2 x 12 display
3
display control RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0
turns display and cursor on; entire display is blank after initialization
4
entry mode set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0
sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DDRAM or CGRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right writes `H'
5
write data to CGRAM or DDRAM RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 1 0 0 0 0
P_
6
write data to CGRAM or DDRAM RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 0 1 0 0 0
PH_
7
| | | write data to CGRAM or DDRAM RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 1 0 0 1 1 PHILIPS_ 0 0 0 0 1 1 1 Product specification HILIPS_ 0 0 0 0 ILIPS M_ 1 1 0 1 writes `M' writes space sets mode for display shift at the time of write PHILIPS_ writes `S'
8
9
entry mode set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0
10
write data to CGRAM or DDRAM RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0
PCF2105
11
write data to CGRAM or DDRAM RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 0
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Jul 30 37 Philips Semiconductors STEP 12 INSTRUCTION DISPLAY | | | write data to CGRAM or DDRAM RS 1 14 RS 0 15 RS 0 16 RS 1 17 RS 0 18 RS 0 19 RS 1 20 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 0 1 1 1 1 MICROKO 0 1 0 0 0 0 MICROKO 0 1 0 0 0 0 ICROCO 0 0 1 1 MICROCO 0 1 1 1 0 0 MICROCO_ 0 1 0 1 0 0 ICROCOM_ 1 1 0 1 | | | return home RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 0 PHILIPS M returns both display and cursor to the original position (address 0) Product specification writes `M' shifts only the cursor to the right shifts the display and cursor to the right writes `C' (correction); the display moves to the left shifts only the cursor position to the left shifts only the cursor position to the left MICROKO writes `O' OPERATION
LCD controller/driver
13
cursor or display shift R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0
cursor or display shift R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0
write data to CGRAM or DDRAM R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0
cursor or display shift R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0
cursor or display shift R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0
write data to CGRAM or DDRAM R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 0
21
PCF2105
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Jul 30 38 Philips Semiconductors Table 8 STEP 1 2 Example of 8-bit operation; 2-line display; using internal reset
LCD controller/driver
INSTRUCTION power supply on (PCF2105 is initialized by the internal reset function) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 1 0 0 0
DISPLAY
OPERATION initialized; no display appears sets to 8-bit operation; selects 2 x 24 display
3
display control RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 1 1 0 _ 0 0 0 0 1 1 0 P_ 0 0 0 0 | | | write data to CGRAM or DDRAM RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 1 0 0 1 1 PHILIPS 0 0 0 0 0 0 PHILIPS 1 1 0 1 PHILIPS_
turns display and cursor on; entire display is blank after initialization
4
entry mode set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0
sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CGRAM or DDRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right
5
write data to CGRAM or DDRAM RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 1
6
7
writes `S'
8
set DDRAM address RS 0 0 1 1
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 _
sets DDRAM address to position the cursor at the head of the 2nd line
9
write data to CGRAM or DDRAM RS 1 0 1 1 0 0
writes `M'
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M_ Product specification | | |
10
PCF2105
11
write data to CGRAM or DDRAM RS 1 0 1 1 0 0 1 1 1 1
PHILIPS
writes `O'
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MICROCO_
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Jul 30 39 Philips Semiconductors STEP 12 RS 0 13 RS 1 14 INSTRUCTION write data to CGRAM or DDRAM 0 0 0 0 0 0 1 1 1 HILIPS 1 1 0 1 | | | return home RS 0 Table 9 STEP 1 2 I2C-bus SA6 0 3 Co 0 4 DB7 0 5 DB7 0 6 DB7 0 start SA4 1 R/W 0 DB5 1 DB5 0 DB5 0 SA3 1 Ack 1 DB4 X DB4 0 DB4 0 DB3 0 DB3 1 DB3 0 DB2 0 DB2 1 DB2 1 DB1 0 DB1 1 DB1 1 DB0 0 DB0 0 DB0 0 Ack 1 _ Ack 1 _ Ack 1 turns display and cursor on; entire display shows character hexadecimal 20 (blank in ASCII-like character sets) Product specification selects 1-line display; SCL pulse during acknowledge cycle starts execution of instruction SA2 0 SA1 1 SA0 0 R/W 0 Ack 1 control byte sets RS and R/W for following data bytes 0 PHILIPS returns both display and cursor to the original position R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MICROCOM (address 0) 0 0 0 0 0 0 1 0 writes `M'; display is shifted to the left; the first and second lines shift together DISPLAY PHILIPS OPERATION sets mode for display shift at the time of write
LCD controller/driver
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MICROCO_
write data to CGRAM or DDRAM 0 1 1 0 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ICROCOM_
15
Example of I2C-bus operation; 1-line display; using internal reset (assuming SA0 = VSS); note 1 INSTRUCTION slave address for write SA5 1 RS 0 DB6 0 DB6 0 DB6 0 DISPLAY OPERATION initialized; no display appears during the acknowledge cycle SDA will be pulled-down by the PCF2105
send a control byte for function set
function set
display control
PCF2105
entry mode set
sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Jul 30 40 Philips Semiconductors STEP 7 8 I2C-bus start INSTRUCTION _ _ SA2 0 SA1 1 SA0 0 R/W 0 Ack 1 _ 1 Ack 1 P_ DB3 0 DB3 1 DB2 0 DB2 0 DB1 0 DB1 0 DB0 0 DB0 0 Ack 1 PH_ Ack 1 | | | | write data to DDRAM DB7 1 17 18 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 1 DB0 1 Ack 1 PHILIPS_ PHILIPS_ R/W 0 DB5 0 R/W 1 Ack 1 PHILIPS DB4 0 Ack 1 PHILIPS DB3 0 DB2 0 DB1 1 DB0 0 Ack 1 PHILIPS sets DDRAM address 0 in AC; also returns shifted display to original position; DDRAM contents unchanged; this instruction does not update the DR PHILIPS_ writes `S' 0 writes `H' 1 DB4 DB4 writes `P'; the DDRAM has been selected at power-up; the cursor is incremented by 1 and shifted to the right DISPLAY OPERATION for writing data to DDRAM, RS must be set to logic 1; therefore a control byte is needed
LCD controller/driver
slave address for write SA6 0 SA5 1 RS 1 DB6 1 DB6 1 SA4 1 R/W 0 DB5 0 DB5 0 SA3
9
send a control byte for write data Co 0
10
write data to DDRAM DB7 1
11
write data to DDRAM DB7 1
12 to 15 16
(optional stop) write (as step 8) control byte Co 1 RS 0 DB6 0 RS 1
I2C-bus
I2C-bus
start + slave address for
19
return home DB7 0
Product specification
PCF2105
20
control byte for read Co 0
DDRAM content will be read from following instructions; the R/W has to be set to logic 1 while still in I2C-bus write mode
21
I2C-bus start
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Jul 30 41 Philips Semiconductors STEP 22 slave address for read SA6 0 SA5 1 SA4 1 SA3 1 SA2 0 SA1 1 SA0 0 R/W 1 Ack 1 INSTRUCTION DISPLAY PHILIPS OPERATION during the acknowledge cycle the content of the DR is loaded into the internal I2C-bus interface and to be shifted out; in the previous instruction neither a `set address' nor a `read data' has been performed; therefore the content of the DR was unknown 8 x SCL; content loaded into interface during previous acknowledge cycle and shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I2C-bus interface 8 x SCL; code of letter `H' is read first; during master acknowledge code of letter `I' is loaded into the I2C-bus interface no master acknowledge; after the content of the I2C-bus interface register is shifted out no internal action is performed; no new data is loaded to the interface register; DR is not updated; AC is not incremented and cursor is not shifted
LCD controller/driver
23
read data: 8 x SCL + master acknowledge; note 2 DB7 X DB6 X DB5 X DB4 X DB3 X DB2 X DB1 X DB0 X Ack 1
PHILIPS
24
read data: 8 x SCL + master acknowledge; note 2 DB7 0 DB6 1 DB6 1 DB5 0 DB5 0 DB4 0 DB4 0 DB3 1 DB3 1 DB2 0 DB2 0 DB1 0 DB1 0 DB0 0 DB0 1 Ack 0
PHILIPS
25
read data: 8 x SCL + no master acknowledge; note 2 DB7 0 Ack 1
PHILIPS
26 Notes
I2C-bus stop
PHILIPS
1. X = don't care. 2. SDA is left at high-impedance by the microcontroller during the READ acknowledge.
Product specification
PCF2105
Philips Semiconductors
Product specification
LCD controller/driver
Table 10 Initialization by instruction; 8-bit interface (note 1) STEP Power-on or unknown state | Wait 2 ms after VDD rises above VPOR | RS 0 DESCRIPTION
PCF2105
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction; function 0 0 0 1 1 X X X X set (interface is 8-bits long) | Wait 2 ms |
RS 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction; function 0 0 0 1 1 X X X X set (interface is 8-bits long) | Wait more than 40 s |
RS 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction; function 0 0 0 1 1 X X X X set (interface is 8-bits long) | | | | BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3)
RS 0 RS 0 RS 0 RS 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 function set (interface is 8-bits long); specify the 0 0 0 1 1 N M X 0 number of display lines R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 display off 0 0 0 0 0 0 0 0 0 0 0 0 | Initialization ends 0 0 0 1 0 0 0 0 1 0 0 I/D 0 1 S R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 clear display R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 entry mode set
Note 1. X = don't care.
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Philips Semiconductors
Product specification
LCD controller/driver
Table 11 Initialization by instruction; 4-bit interface; not applicable for I2C-bus operation STEP Power-on or unknown state | Wait 2 ms after VDD rises above VPOR | RS 0 DESCRIPTION
PCF2105
R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction; function set (interface is 8-bits long) 0 0 0 1 1 | Wait 2 ms |
RS 0
R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction; function set (interface is 8-bits long) 0 0 0 1 1 | Wait 40 s |
RS 0
R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction; function set (interface is 8-bits long) 0 0 0 1 1 | | | BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) 0 0 M 0 0 0 0 0 1 | Initialization ends 1 1 0 0 0 0 0 0 I/D 0 0 0 0 0 0 0 0 S
RS 0 RS 0 RS 0 RS 0 0 RS 0 0 RS 0 0
R/W DB7 DB6 DB5 DB4 function set (set interface to 4-bits long); interface is 8-bits long 0 0 0 0 0 0 0 0 0 0 0 N 0 1 0 1 0 0 R/W DB7 DB6 DB5 DB4 function set (interface is 4-bits long) R/W DB7 DB6 DB5 DB4 specify number of display lines and voltage generator characteristic R/W DB7 DB6 DB5 DB4 display off
R/W DB7 DB6 DB5 DB4 clear display
R/W DB7 DB6 DB5 DB4 entry mode set
1998 Jul 30
43
Philips Semiconductors
Product specification
LCD controller/driver
18 BONDING PAD LOCATIONS
PCF2105
R13
R10
C11
C13
C14
C15
C18
C21
R14
C12
C19
R11
C10
R12
R9
C2
C3
C5
C4
C1
C6
C7
C8
86 85 84 83 82 81
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
C9
handbook, full pagewidth
C16
C17
C20
C22
R15 R16 R25 R26 R27 R28 R1 R2 R3 R4 SCL E RS 5.63 mm
87 88 89 90 91 92 93 94 95 96 97 98 99
58 57 56 55 54 53 52 51 50 49 48 47 46 45
C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53
R/W 100 T1 101 DB7 102 DB6 103 DB5 104 DB4 105 DB3 106 DB2 107 DB1 108 DB0 109 SDA 110
x 0 0 y
44 43 42 41 40 39
PCF2105
38 37 36 35 34 33 32 31 30 29
VLCD 111
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
28
R5
R32
R30
R23
R20
R18
R17
C60
C57
OSC
SA0
VSS
R31
R19
C56
R24
R21
R29
R22
VDD
5.10 mm
C59
C58
C55
C54
R8
R7
R6
MGK857
Chip dimensions: approximately 5.10 x 5.63 mm. Gold bump dimensions: approximately 89 x 89 x 25 m.
Fig.30 Bonding pad locations.
1998 Jul 30
44
Philips Semiconductors
Product specification
LCD controller/driver
Table 12 Bonding pad locations (dimensions in m). All x/y coordinates are referenced to centre of chip, see Fig.30. SYMBOL OSC VDD SA0 VSS R8 R7 R6 R5 R32 R31 R30 R29 R24 R23 R22 R21 R20 R19 R18 R17 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 1998 Jul 30 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 x -2184.5 -2024.5 -1864.5 -1704.5 -1339 -1179 -1019 -859 -699 -539 -379 -219 -59 101 261 421 581 741 901 1061 1221 1381 1541 1701 1861 2021 2181 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 y -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2637 -2445 -2285 -2125 -1965 -1805 -1645 -1485 -1325 -1165 -1005 -845 45 SYMBOL C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 PAD 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 x 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2350 2185 2025 1865 1705 1545 1385 1225 1065 905 745 585 425 265 105 -55 -215 -375 -535
PCF2105
y -685 -525 -365 -205 -45 115 275 435 595 755 915 1075 1235 1395 1555 1715 1875 2035 2195 2355 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
SYMBOL C4 C3 C2 C1 R9 R10 R11 R12 R13 R14 R15 R16 R25 R26 R27 R28 R1 R2 R3 R4 SCL E RS R/W T1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDA VLCD RECPAT `F' RECPAT `C' RECPAT `C'
PAD 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 - - -
x -695 -855 -1015 -1175 -1385 -1545 -1705 -1865 -2025 -2185 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2349 -2327.5 -2027.5 1982.5
y 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2637.5 2308 2148 1988 1828 1668 1508 1348 1188 1028 868 632 472 312 142 -34 -233 -393 -668 -828 -1103 -1263 -1538 -1698 -1933 -2453 2427.5 -2512.5 2297.5
1998 Jul 30
46
Philips Semiconductors
Product specification
LCD controller/driver
19 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF2105
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Jul 30
47
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/02/pp48
Date of release: 1998 Jul 30
Document order number:
9397 750 04198

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